Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs), may be programmed with configuration data to provide various user-defined features. For example, desired functionality may be achieved by programming a configuration memory of a PLD with an appropriate configuration data bitstream.
Unfortunately, the transfer of such configuration bitstreams to PLDs or external memory devices is often cumbersome. In particular, the loading of large uncompressed configuration data bitstreams can result in undesirable delays that are unacceptable in various applications. This can be particularly problematic for implementations where uncompressed configuration data bitstreams are loaded into a PLD from an external device each time the PLD is booted.
However, existing data compression methods are generally not well adapted for use with the particular data formats associated with configuration data bitstreams. For example, in one approach, bulk erase bytes (i.e., bytes comprised of eight erase bits) appearing within an 8 byte sequence of configuration data may be represented by an 8 bit header identifying the location of the bulk erase bytes within the sequence. In another approach, Huffman coding techniques may be used to encode bulk erase bytes and repetitive bytes appearing within a sequence or row of configuration data.
Unfortunately, when used alone, these approaches may not provide efficient compression of configuration data unless large numbers of bulk erase bytes or individual repetitive bytes are present. In particular, they do not provide a sufficiently generic approach to compression that may be used with a variety of different configuration data bitstreams. Accordingly, there is a need for an improved approach to the compression of configuration data bitstreams for use with PLDs.